1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a gate array or an embedded cell array (ECA), and more particularly, to a clock driver circuit furnished in that semiconductor integrated circuit device.
2. Background Art
In semiconductor integrated circuit devices including gate arrays and embedded cell arrays (ECA), their core regions have two kinds of macro cells formed therein, i.e., a plurality of macro cells acting as logic circuits (such as AND and/or OR circuits), and a plurality of macro cells acting as internal circuits (such as flip-flop circuits), each kind requiring a clock signal. Clock driver circuits are furnished to supply clock signals to the multiple internal circuits.
In recent years, semiconductor integrated circuit devices have been required to be larger in scale and faster in operation than ever before. The requirements have prompted a proposal, among others, to increase the number of internal circuits in each semiconductor integrated circuit device and to supply the internal circuits with clock signals more efficiently with smaller clock skews. FIG. 14 is a plan pattern view of a conventional semiconductor integrated circuit device based on that proposal. This conventional integrated circuit is disclosed illustratively in Japanese Patent Laid-Open Publication No. Hei 7-14994.
In FIG. 14, a semiconductor substrate 100 comprises an internal integrated circuit group (core region) 101 and oppositely positioned peripheral circuit groups (buffer regions) 102. A first signal driver circuit (clock input driver) 103 is located in one of the oppositely positioned peripheral circuit groups 102. The first signal driver circuit amplifies a reference signal (clock signal). A plurality of second signal driver circuits (column drivers) 104 are located in another one of the oppositely positioned peripheral circuit groups 102 contiguous to the first peripheral circuit group. The second signal driver circuits 104 are positioned at both ends of the internal integrated circuit group 101 contiguous to the peripheral circuit groups 102. First signal lines 105 connect the first and second signal driver circuits 103 and 104. Second signal lines 106 connect the second signal driver circuits 104 to the internal integrated circuit group 101.
In the setup described above, the first signal driver circuit 103 amplifies the reference signal. The amplified reference signal is fed to the second signal driver circuits 104 via the first signal lines 105 arranged symmetrically as viewed from the first signal driver circuit 103. The second signal driver circuits 104 amplify the reference signal allowing a uniform reference signal to be supplied onto the second signal lines 106 wired in a comb-like manner. This makes it possible to minimize fluctuations in the reference signal reaching the internal integrated circuit group 101. Using the reference signal with reduced signal delays, i.e., with reduced clock skews, the internal integrated circuit group 101 processes various signals.
Another technique proposed in connection with the semiconductor integrated circuit device described above involves installing an easy-to-install clock driver circuit of high driving capacity without increasing the area of the semiconductor substrate. FIG. 15 is a partial plan pattern view of another conventional semiconductor integrated circuit device based on the above proposal and is disclosed illustratively in Japanese Patent Laid-Open Publication No. Hei 6-236923.
In FIG. 15, a macro cell layout region 201 is disposed on the semiconductor substrate 100. A power supply line 202a provides a supply potential VDD. The power supply line 202a is composed of a second aluminum wiring layer that is formed perpendicularly to the macro cell layout region 201. A ground line 202b provides a ground potential GND. The ground line 202b is also made of the second aluminum wiring layer formed perpendicularly to the macro cell layout region 201 and in parallel with the power supply line 202a. The ground line 202b and power supply line 202a constitute a power supply line pair. A power supply line 203a is located above the macro cell layout region. The power supply line 203a is connected to the power supply line 202a via through holes 204a, and is made of a first aluminum wiring layer. A ground line 203b is located below the macro cell layout region. The ground line 203b is connected to the ground line 202b via through holes 204b, and is made of the first aluminum wiring layer.
Also in FIG. 15, a macro cell 205 is located below the power supply lines in the macro cell layout region, and has functions including that of driver circuits. An input signal line 206 is connected to the input node of the macro cell 205 via a through hole 207 in order to input signals to that cell. Made of the second aluminum wiring layer, the input signal line 206 extends between the power supply line 202a and the ground line 202b in parallel therewith. An output signal line 208 is connected to the output node of the macro cell 205 via through holes 209 in order to output signals from that cell. Composed of the second aluminum wiring layer, the output signal line 208 also extends between the power supply line 202a and the ground line 202b in parallel therewith.
In the conventional semiconductor integrated circuit device of the type outlined above, the macro cell 205, having functions including that of driver circuits, is located below the power supply line pair made up of the power supply line 202a and ground line 202b. This setup facilitates the supply of power to the macro cell 205 and helps reduce the area occupied by the macro cell 205 on the semiconductor substrate.
As semiconductor integrated circuit devices are required to be larger in scale and faster in operation than ever before, there is a growing need for a clock driver circuit offering a higher-than-ever driving capability with smaller clock skews.